PARALLEL ANALOG-TO-DIGITAL CONVERTER WITH TIME-COMPRESSION OF SIGNALS

Abstract

The paper presents a method for increasing the resolution of parallel analog-to-digital converters (ADCs) with time compression of signals. It is established that analog-to-digital conversion of signals in parallel ADCs with time compression of output signals is performed in separate channels with non-identical bandwidths. Ultimately, this leads to a decrease in resolution when converting input signals.

The difference in the bandwidths of parallel ADC channels is due to the features of the sample and store circuits (SSCs), which are installed at the inputs of each ADC. SSCs are necessary to reduce dynamic errors that arise when discretizing time-varying analog signals. The functioning of SSCs is based on the principle of fixing the instantaneous value of the input signal for the time required for further conversion in the ADC. The input circuits of SSCs can be represented as low-pass filters, in which there is a spread of the parameters of resistors and capacitors that determine the bandwidth of the i-th ADC channel. The passband adjustment in each ADC channel is carried out by switching resistors in the input circuits of the converter.

To reduce the errors of non-identity of the passbands, it is proposed to introduce a reference additional ADC (АADC), which operates with a lower sampling frequency. In the operating mode, one of the ADC channels is calibrated. At the same time, the reference АADC operates with a sampling frequency that allows it to operate in phase with one of the working ADCs in each conversion cycle.

A structural diagram of a parallel ADC (PADC) based on time compression of signals with correction of the passbands of individual ADC channels has been developed. The PADC operates in two modes: calibration and working with correction. In the calibration mode, a sinusoidal signal is supplied to the inputs of all PADC channels from the output of the test signal generator through an analog switch. The array of digital data from the output of the ADC is accumulated in a buffer storage device. Then, the accumulated array is fed to a computer via an interface adapter and a USB bus, where the errors of non-identity of the bandwidths of the ADC channels are calculated. Each ADC channel contains a digital-to-analog converter at the input, which performs the function of a digital potentiometer for the input signals of the SSC. The calculated transfer coefficients from the outputs of the control unit are fed to the corresponding ADC channels.

Analysis of the ADC efficiency showed that by adjusting the bandwidths of individual channels of a 12-bit PADC, it is possible to improve the resolution in the low-frequency band by 0,5 bits, and in the high-frequency band by 1,9 bits.