DEVELOPMENT OF THE ARCHITECTURE OF THE MULTICHANNEL CONVEYOR RADIO RECEIVER BASED ON FPGA

Abstract

Modern telecommunication networks are facing increasingly complex challenges due to the constant increase in the density of electronic devices, the active use of a wide range of radio frequencies and the need to ensure a high level of electromagnetic compatibility. Traditional radio reception systems using single-channel or simple multi-channel circuits no longer meet modern requirements, as they are limited in the ability to simultaneously monitor several frequency bands and quickly adapt to dynamic changes in environmental conditions. This creates a need for further development of existing approaches to multi-channel radio reception and technical solutions for their implementation using software-defined radio (SDR) technology. The article analyzes in detail the main methods of multichannel radio reception, in particular, the time division multiplexing (TDM) method, the frequency division multiplexing (FDM) method, the multichannel digital radio reception method using frequency selection and the pipeline digital signal processing method, and identifies their advantages and disadvantages, which made it possible to justify the choice of the multichannel pipeline approach as the basic one for use in the study and, as a result, to propose an architecture of a multichannel pipeline radio receiver based on FPGA with increased efficiency in terms of sensitivity and performance. The proposed technical solution using an IQ mixer provides effective transfer of frequency ranges to the baseband, which allows for high-quality digital reception of signals without significant deterioration of their characteristics. At the same time, it was found that the use of IQ mixers is accompanied by a number of disadvantages, such as imbalance of IQ channels and DC offset, which requires the use of additional compensation algorithms. The effectiveness of using digital CIC and FIR filters to compensate for the unevenness of the frequency response of the radio receiver has been verified. These developments, together with the architecture, provide the basis for further research and implementation of a multi-channel pipelined radio receiver based on FPGA.